In the field of high speed CMOS circuits, there have been several efforts to reduce the delay of high fan-in circuits by using the dynamic differential circuit and sense-amplifier (sense-amp) together. Recent circuit styles use differential pass-transistor logic for the logic evaluation tree.
FIG. 1A shows in simplified form, a prior art circuit diagram, including sense amp 1 and logic evaluation circuit 15′. The CLK signals are applied to equilibrate the OUT and OUT# nodes (using the convention that OUT# means the logic complement of OUT) of the sense-amp to ground and the delayed CLK signal opens a current path to VDD. In the precharge mode (when CLK is high) every internal nodes in the logic tree 15′ is floating. In the evaluation mode (When CLK is low), pass-gate logic tree circuit 15′ performs the logic analysis and applies the differential input to nodes Q and Q#. This differential input causes a corresponding difference of currents through the two NMOS transistors 16′. Sense amp 1 will respond to the differential signal once the difference exceeds the noise level and will drive nodes OUT and OUT# to the rails.